Analog-to-Digital Converter (ADC)

Modern scientific cameras use column-parallel ADC architectures, where each column of pixels has its own converter, enabling simultaneous readout across the sensor. ADC bit depth (typically 12-16 bits) determines the number of digitization levels. ADC speed (in megasamples/second) limits the maximum frame rate. ADC noise contributes to the camera's total read noise.

The ADC should have enough bit depth to fully digitize the sensor's dynamic range. If dynamic range (well depth / read noise) exceeds 2^N, the ADC is the bottleneck — it discards information the sensor captured.

The ADC is often invisible to the user, but its specifications have direct consequences. An sCMOS camera with a 30,000 e⁻ well and 1.5 e⁻ read noise has ~14.3 stops of dynamic range — requiring at least a 15-bit ADC to avoid being the limiting factor. Many cameras offer 16-bit ADC, providing comfortable headroom.

Some cameras offer switchable gain modes: 'high dynamic range' mode uses the full well with 16-bit ADC, while 'high sensitivity' mode uses lower gain with 12-bit ADC for faster readout. Understanding the ADC tradeoff helps choose the right mode for each experiment.